This invention relates to a semiconductor device which is formed on a semiconductor wafer and relates to a method of testing whether or not the semiconductor device is acceptable. In particular, this invention relates to a semiconductor device which includes an unvolatile memory and relates to a method of testing whether or not the semiconductor device is acceptable.
In a semiconductor device manufacturing process, a plurality of semiconductor devices are formed on a semiconductor wafer in a lump. Subsequently, these semiconductor devices are individually tested whether or not each of semiconductor devices has a predetermined electric characteristic and whether or not executes a predetermined function correctly. Namely, each of the semiconductor devices is tested to ascertain quality. Afterwards, the semiconductor devices are cut away from semiconductor wafer into chips or pellets which have the semiconductor devices, respectively. At this time, the semiconductor devices are classified into acceptable group and nonacceptable group on the basis of results of the test, i.e. the quality. The semiconductor devices of the acceptable group are sent to a later process, for example, a packaging process, while the semiconductor devices of the nonacceptable devices are not send to the later process.
Some methods have been proposed to test the semiconductor devices. For example, there is a method which is described in Japanese Unexamined Patent Publication No. 322441/1992. In this method, the semiconductor devices tests themselves all at once in reply to a source voltage and a self-test starting signal. In this case, the source voltage and the self-test starting signal are supplied from a external tester through probes which are connected to the external tester and which are brought into contact with connecting pads connected to the semiconductor devices on the semiconductor wafer. Results of the test are transmitted to the external-tester through the probes and are memorized in a memory of the external tester.
Moreover, there is another method which is described in an Japanese Unexamined Patent Publication No. 283641/1987. In this method, the semiconductor devices test themselves at a time in reply to a source voltage. The source voltage is supplied to the semiconductor devices through a voltage supply line and a ground line both of which are wired formed on the semiconductor wafer and which are connected to the semiconductor devices. Each of the semiconductor devices is connected to an output terminal and supplies a result signal of the test through the output terminal. The result signal is gathered by the external tester. Similar methods are described in Japanese Unexamined Patent Publication No. 159149/1991, Nos. 320044/1992, and 257650/1990.
On the other hand, it is described in Japanese Unexamined Patent Publication No. 90549/1990 to give an unvolatile memory element to each of the semiconductor devices. The unvolatile memory element is used for memorizing a result obtained by testing each of the semiconductor devices. The result is written into the unvolatile memory element by the external tester to select acceptable devices before a package process. Similar technique is also disclosed in Japanese Unexamined Patent Publication No. 192344/1985.
In addition, it is further disclosed in an Japanese Unexamined Patent Publication No. 10230/1984 to connect a diode and a resistor to each of the semiconductor devices through a common wiring pattern for voltage supply. With this structure, a normal a voltage is kept even when a certain semiconductor device is shorted and much unusual electric current flows through the resistor. Therefore, the normal voltage is given to the other semiconductor devices than the shorted semiconductor device.
Other methods and other techniques for testing semiconductor devices one by one or two by two are disclosed in Japanese Unexamined Patent Publication Nos. 217625/1987, 230086/1994, 171136/1987, 7136/1982, and 171137/1987.
In any case, results of the test must be gathered one by one from the semiconductor devices by the external tester. Therefore, either complicated lines on the semiconductor wafer or many probes connected to the external tester are necessary to gather the results. Moreover, it takes a long time to carry out the test because the results must be gathered one by one as mentioned above.